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ASIC Design Engineer


Posted by: Julianna Raffa - NESC Staffing <jraffa@nesc.com> on July 08, 2018 at 00:04:02. Click here to reply to this post via Email.Click here for help with email link

Contract / Temp to Direct / Direct Hire: Contract
City: Cedar Rapids
State: Iowa
Country: United States
Zip or Postal Code: 52402

ASIC Design Engineer:

Requirements capture, ASIC/FPGA digital architecture and design using RTL, timing analysis and closure, verification and system integration
RTL coding and simulation in VHDL or Verilog
Testbench development for the verification of RTL blocks using VHDL or SystemVerilog
Recommend new tools and practices for continuous improvement in the group's ASIC/FPGA design flow

2 year contract!!






      

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