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Senior Verification Engineer - Rate is open + per diem

Posted by: Von Mizener Consulting <> on May 28, 2017 at 00:04:01. Click here to reply to this post via Email.Click here for help with email link

Contract / Temp to Direct / Direct Hire: Contract
City: Santa Clara
State: California
Country: United States

Job Title: Senior Verification Engineer
Seek a talented Senior
Verification Engineer for regular employment or temporary employment
to fill a critical role developing and enhancing SystemVerilog UVM
testbenches for CPU/CPU chips and ship sets for graphics applications.

* 7+ years relevent experience verifying ASICs and FPGAs.
* 1-2 projects creating and utilizing SystemVerilog UVM testbenches.
* 1-2 projects verifying Memory Subsystems and cache based systems
including but not limited to MMU (Memory Management Unit), Page
Tables, and Cache Coherency protocols.
* UNIX scripting experience (TCL, Perl, Python).

* Functional coverage experience a plus.
* Experience with SystemVerilog OVM and VMM a plus.
* Specman 'e experience a plus.
* C, C++, SystremC, and Object Oriented Programming experience a plus.

* Strong English verbal and written communication skills required.

Education Requirements:
* BSEE, BSCS, or equivalent experience in closely related field.

Job Location
* Santa Clara, CA

Job Duration
9-12+ months

key words:
* GPU, CPU, HVL, Hardware Verification Language, Vera, Specman, 'e,
Constrained Random, SoC Verification, Verification Plans, Assertion
Based Verifiction, ABV, Code coverage, Coverage Points, Coverage
Bins, Functional Coverage Points, Functional Coverage Bins, Coverage
Closure, Object Oriented, OO, Aspect Oriented, Multiprocessing,
Multi-processing, Snooping, Write-back cache, Write-through cache,
Directory-based cache, Symmetric multiprocessing, Asymmetric
multiprocessing, Shared memory, Distributed shared memory, UMA,
NUMA, Computer cluster, Multi-thread, multithread, MSI, MESI.


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