Contract / Temp to Direct / Direct Hire: Contract
Country: United States
Seeking a talented Principal Verification Engineer for regular or temporary employment
to fill a critical role developing and enhancing testbenches written
in C/C++ and SystemVerilog, performing SoC level integration and
testing, and debugging at the SoC level.
- SOC level Integration and functional verification of a complex CPU/GPU SOCs.
- Work closely with a team members to understand and verify new and
existing design features.
- Debug of Verilog RTL and System Verilog & C/C++ testbench at the SOC-level.
- One or more of the following:
o Measure performance metrics against specification.
o Integrate Verification IP and maintain working verification environment.
o Verify complex features include coherency and power related features.
- 10 or more years of proven SOC level verification experience on
- Knowledgeable in C/C++, OO programming, Verilog, System Verilog, and
scripting languages (Perl, etc)
- Familiar with constrained random verification
- Excellent debug skills, ability to analyze and isolate
design/testbench issues using various techniques including waveforms
and log files.
- Familiar with hardware modeling and/or assertion-based verification
- Experience in one or more of the following areas:
- Measuring feature performance metrics against specification is
- SOC Level Verification IP integration
- Data Coherency Feature Verification in complex data path SOCs
- Power aware simulations which may include gate level verification of
power aware features.
- Background in GPU/CPU architecture along with significant memory
system and /or SoC architecture experience is important.
* Strong English verbal and written communication skills required.
* BSEE, BSCS, or equivalent experience in closely related field.
* Boxboro, MA
* GPU, CPU, HVL, Hardware Verification Language, Vera, Specman, 'e,
Power Aware, Constrained Random, SoC Verification, Verification
Plans, Assertion Based Verifiction, ABV, Code coverage, Coverage
Points, Coverage Bins, Functional Coverage Points, Functional
Coverage Bins, Coverage Closure, Object Oriented, OO, Aspect
Oriented, Multiprocessing, Multi-processing, Snooping, Write-back
cache, Write-through cache, Directory-based cache, Symmetric
multiprocessing, Asymmetric multiprocessing, Shared memory,
Distributed shared memory, UMA, NUMA, Computer cluster,
Multi-thread, multithread, MSI, MESI.
2 page view(s)
Thinking about applying for this position?
Please make sure that you meet the minimum requirements indicated for the job before you apply (see user agreement). If you are qualified, then use either the email link (near top of post) or the application link (near bottom of post) to apply, whichever is provided.
Roadtechs.com notice to workers thinking about a career in nuclear power:
All nuclear power plant employees are subject to background, financial and criminal history checks before they are granted access to any nuclear power facility and these checks are repeated at regular intervals. Additionally, new hire drug and alcohol screening is mandatory and all sites perform random drug and alcohol screening.
© Copyright - Roadtechs®, LLC. All rights reserved. No reproduction of any part of this website may be sold or
distributed for commercial gain nor shall it be modified or incorporated in any other work, publication, or website.
Use of this site implies compliance with the Roadtechs User Agreement.